1. Field of the Invention
The present invention relates to a display device driving circuit, a control method thereof, and a display device using the same. More specifically, the present invention relates to reducing power consumption.
2. Description of Related Art
Recently, a display device has been used for a portable terminal, and driven by a built-in battery of the portable terminal in many cases. Further, the number of outputs of a data-line driving circuit installed in one IC chip has been increased even in a display device that can use a commercial power supply. Therefore, there have been more demands to implement still lower power consumption for the data-line driving circuit of the display device.
FIG. 1 is a block diagram showing a typical data-line driving circuit of a display device. The data-line driving circuit is generally called a driver IC. As shown in FIG. 1, a driver IC 10 includes a serial-parallel conversion circuit 11, a latch circuit 12, a level shifter circuit 13, a grayscale voltage output circuit 14, a digital-analog conversion circuit 15, and an output circuit 16. In FIG. 1, a clock signal/bit data section 17 outputs bit data. The serial-parallel conversion circuit 11 receives the bit data, and outputs n-bit parallel data. A logic setting input signal section 18 controls the serial-parallel conversion circuit 11 and the latch circuit 12 by outputting a strobe signal to write the parallel data outputted from the serial-parallel conversion circuit 11 into the latch circuit 12. The parallel data written to the latch circuit 12 appears on latch data lines, and their voltage levels are shifted by the level shifter circuit 13. The n-bit parallel data outputted from the level shifter circuit 13 are supplied to the digital-analog conversion circuit 15. The grayscale voltage output circuit 14 generates a grayscale voltage using a γ correction power supply, and outputs the generated grayscale voltage to the digital-analog conversion circuit 15 via a grayscale voltage line. When a voltage range on a positive side of the driver output differs from that on a negative side of the driver output (when a common voltage is constant), the grayscale voltage output circuit 14 generates 2n number of grayscale voltages for the positive side and 2n number of grayscale voltages for the negative side and outputs those voltages. When executing a common inversion drive, the grayscale voltage output circuit 14 generates 2n number of grayscale voltages and outputs those voltages. The digital-analog conversion circuit 15 selects one of the grayscale voltages based on the n-bit parallel data. The output circuit 16 outputs the grayscale voltage selected by the digital-analog conversion circuit 15 as an output of the driver IC.
FIG. 2 is a circuit diagram showing a typical digital-analog conversion circuit and its related circuit. In FIG. 2, the level shifter circuit 13 includes n number of level shifters, receives n-kinds of complementary signals, shifts the voltages thereof, and outputs the n-kinds of complementary signals. A level shifter 20 that level-shifts a first bit of the complementary signal receives a signal L1 and an inverted signal L1B thereof, and outputs a signal S1 and an inverted signal S1B thereof. When the input signal L1 of the level shifter 20 is the High level, the inverted signal L1B is Low, the output signal S1 is the High level, and the inverted output signal S1B is Low. Further, when the input signal L1 of the level shifter 20 is Low, the inverted signal L1B is the High level, the output signal S1 is Low, and the inverted output signal S1B is the High level. The digital-analog conversion circuit 15 includes transistors arranged in matrix, and selects prescribed grayscale voltages from the 2n number of grayscale voltages based on the n-kinds of complementary signals. In FIG. 2, there are 2n number of grayscale voltage lines, and 2n number of grayscale voltages are supplied to the digital-analog conversion circuit 15. In the meantime, the digital-analog conversion circuit 15 is connected to the level shifter circuit 13 via 2n number of grayscale signal lines that are in pairs of two each. For example, when the output signal S1 of the level shifter 20 is the High level, a transistor 22 is turned on so that the grayscale voltage of a grayscale voltage line 23 is selected. At this time, the inverted output signal S1B of the level shifter 20 becomes Low. Thus, a transistor 24 is turned off so that the grayscale voltage of a grayscale voltage line 25 is not selected. In the meantime, when the output signal S1 of the level shifter 20 is Low, the transistor 22 is turned off so that the grayscale voltage of the grayscale voltage line 23 is not selected. At this time, the inverted output signal S1B of the level shifter 20 becomes the High level. Thus, the transistor 24 is turned on so that the grayscale voltage of the grayscale voltage line 25 is selected. Therefore, 2n-1 number of grayscale voltage lines are to be selected from the 2n number of grayscale voltage lines, based on the complementary signals flown on a pair of grayscale signal lines connected to the first-bit level shifter 20. Further, 2n-2 number of grayscale voltage lines are to be selected from the 2n-1 number of grayscale voltage lines that are selected based on the first-bit complementary signals, based on the second-bit complementary signals flown on a pair of grayscale signal lines connected to the second-bit level shifter. In the same manner, 2n-3 number of grayscale voltage lines are to be selected from the 2n-2 number of grayscale voltage lines that are selected based on the first-bit and second-bit complementary signals, based on the third-bit complementary signals. Ultimately, a single grayscale voltage line is selected based on the n-kinds of complementary signals flown on the n-pairs of grayscale signal lines that are connected to the n number of level shifters. This grayscale voltage of the grayscale voltage line is outputted to the output circuit 16 as an analog signal.
As a related art, a data-line driving circuit of a display device is disclosed in Japanese Laid-Open Patent Application JP 2003-248466 A, which is designed to reduce the power consumption on a digital-analog conversion circuit. In this related art, the digital-analog conversion circuit in an LCD driver internal circuit is disclosed. The digital-analog conversion circuit has a function of judging an input signal from a level shifter circuit and recovering electric charges on output wirings depending on the sum total of the number of wirings whose logics are inverted. That is, when there are a large number of wirings whose logics are to be inverted in sequential digital grayscale signals, a pair of an output line and an inverted output line of a level shifter is short-circuited so as to recover the electric charges. For example, regarding the level shifter 20 shown in FIG. 2, the wiring of the output signal S1 and the wiring of the inverted output signal S1B are short-circuited to set output potentials of the both to a middle level of an “H” (High) level and an “L” (Low) level. With this, when the logic is to be inverted from the “H” level to the “L” level, it can be changed from the middle level to the “L” level. Meanwhile, when the logic is to be inverted from the “L” level to the “H” level, it can be changed from the middle level to the “H” level. This makes it possible to reduce the power consumption.
We have now discovered the following fact. The electric charge recovery function described in the related art of JP2003-248466A short-circuits the output wirings of the level shifter circuit while having the grayscale voltage continuously supplied to the digital-analog conversion circuit. In this case, an abnormal current is generated at the time of recovering the electric charge, which may result in having extra power consumption. FIG. 3 is a circuit diagram showing a problem of the related art technique. As shown in FIG. 3, at the time of recovering the electric charges, a switch 31 is turned on, and output wirings 32 and 33 of a level shifter 30 in a pair are short-circuited. It is expected for the voltage of the short-circuited output wiring 32, 33 to be in a value close to the middle of the voltages previously-applied to the output wirings 32, 33. However, the voltage normally exceeds a threshold voltage of transistors 34, 35. Since this voltage is applied to gates of the transistors 34 and 35, both of the transistors 34 and 35 are turned on. With this, the transistors 34 and 35 become electrically conductive, and grayscale voltages of different grayscales appear on grayscale voltage lines 36 and 37. That is, when recovering the electric charges by short-circuiting each of the pairs of the output wirings of the level shifter circuit, all the transistors within the digital-analog conversion circuit are turned on. This may result in having an abnormal current, shown with a dotted line in FIG. 3, generated between the different grayscale voltages. With this related art technique, there is a possibility of losing the function of reducing the power consumption by recovering the electric charges, because of the abnormal current.